US 12,255,178 B2
Mirror image of geometrical patterns in stacked integrated circuit dies
Ido Bourstein, Pardes Hana— Karkur (IL)
Assigned to Mellanox Technologies, Ltd, Yokneam (IL)
Filed by Mellanox Technologies, Ltd., Yokneam (IL)
Filed on Jan. 26, 2022, as Appl. No. 17/584,450.
Prior Publication US 2023/0238358 A1, Jul. 27, 2023
Int. Cl. H01L 25/065 (2023.01); G03F 1/20 (2012.01); H01L 23/00 (2006.01)
CPC H01L 25/0657 (2013.01) [G03F 1/20 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A. A set of reticles, the set comprising:
at least a first mask for producing a first integrated circuit (IC) die, the first mask comprising a first set of elements that are arranged in a first geometrical pattern and are configured to attenuate a beam impinging thereon; and
at least a second mask for producing a second IC die, the second mask comprising a second set of the elements that are (i) arranged in a second geometrical pattern that is a mirror image of the first geometrical pattern and (ii) configured to attenuate the beam impinging thereon.