US 12,255,177 B2
Stacked semiconductor device
Yo Sep Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Incheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 10, 2021, as Appl. No. 17/548,186.
Claims priority of application No. 10-2021-0063927 (KR), filed on May 18, 2021.
Prior Publication US 2022/0375900 A1, Nov. 24, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/48225 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stacked semiconductor device comprising:
a plurality of stacked semiconductor dies including a lowermost semiconductor die, an uppermost semiconductor die and intermediate semiconductor dies located between the lowermost semiconductor die and the uppermost semiconductor die;
a first power line arranged under the lowermost semiconductor die and electrically connected to the lowermost semiconductor die;
a second power line arranged on an upper surface of the uppermost semiconductor die and electrically connected to the uppermost semiconductor die; and
an external connection line electrically and directly connecting the first power line and the second power line so that power supplied to the lowermost semiconductor die through the first power line is directly supplied to the uppermost semiconductor die without passing through the intermediate semiconductor dies.