US 12,255,176 B2
Scalable architecture for reduced cycles across SOC
Javier A. DeLaCruz, San Jose, CA (US); and Richard E. Perego, Thornton, CO (US)
Assigned to Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR TECHNOLOGIES LLC, San Jose, CA (US)
Filed on Jul. 5, 2023, as Appl. No. 18/347,510.
Application 18/347,510 is a continuation of application No. 16/677,213, filed on Nov. 7, 2019, granted, now 11,862,602.
Prior Publication US 2023/0369286 A1, Nov. 16, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/481 (2013.01); H01L 24/33 (2013.01); H01L 2224/32225 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of forming a microelectronic assembly for a mesh network of a plurality of processor cores, the microelectronic assembly, comprising:
providing a plurality of orthogonal connections in a first element, the orthogonal connections each extending in one of first and second horizontal directions, the first and second horizontal directions oriented orthogonal to one another;
providing a plurality of oblique connections in a second element; the oblique connections each extending in one of third and fourth horizontal directions, the third and fourth horizontal directions each oriented at an oblique angle relative to the first and second directions; and
directly hybrid bonding the first element to the second element such that the orthogonal connections and the oblique connections interconnect a plurality of network nodes, the network nodes connected to the plurality of processor cores in the mesh network, wherein the mesh network permits an electrical signal to travel from any one of the network nodes to any other one of the network nodes through the orthogonal connections and/or oblique connections.