US 12,255,173 B2
Chip package structure
Ling-Wei Li, Hsinchu (TW); Jung-Hua Chang, Hsinchu (TW); and Cheng-Lin Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 24, 2023, as Appl. No. 18/518,790.
Application 18/518,790 is a continuation of application No. 17/884,200, filed on Aug. 9, 2022, granted, now 11,855,039.
Application 17/884,200 is a continuation of application No. 16/995,183, filed on Aug. 17, 2020, granted, now 11,456,276, issued on Sep. 27, 2022.
Application 16/995,183 is a continuation of application No. 16/454,435, filed on Jun. 27, 2019, granted, now 10,770,427, issued on Sep. 8, 2020.
Prior Publication US 2024/0088090 A1, Mar. 14, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/482 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01)
CPC H01L 24/81 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/76816 (2013.01); H01L 21/76871 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/4824 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 23/562 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/02333 (2013.01); H01L 2224/03914 (2013.01); H01L 2224/04 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a first substrate;
a conductive via structure passing through the first substrate;
a barrier layer over a surface of the first substrate;
an insulating layer over the barrier layer;
a conductive pad over the insulating layer, wherein the conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure;
a conductive bump over the conductive pad;
a second substrate, wherein the first substrate is bonded to the second substrate through the conductive bump; and
an underfill layer between the first substrate and the second substrate, wherein a second portion of the underfill layer extends into the first portion of the conductive pad.