US 12,255,164 B2
Structure and method for isolation of bit-line drivers for a three-dimensional NAND
Liang Chen, Hubei (CN); Wei Liu, Hubei (CN); and Cheng Gan, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Jun. 27, 2022, as Appl. No. 17/850,276.
Application 17/850,276 is a division of application No. 16/729,821, filed on Dec. 30, 2019, granted, now 11,538,780.
Application 16/729,821 is a continuation of application No. PCT/CN2019/110978, filed on Oct. 14, 2019.
Prior Publication US 2022/0328441 A1, Oct. 13, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/18 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 21/31053 (2013.01); H01L 21/76224 (2013.01); H01L 23/528 (2013.01); H01L 24/50 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H01L 23/5226 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80001 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming, on a first side of a first substrate, a peripheral circuitry comprising peripheral devices and a first interconnect layer, wherein each peripheral device of the peripheral devices is formed within a well in the first substrate;
forming shallow-trench-isolations extending into the first substrate from the first side;
forming, on a second substrate, a memory array comprising memory cells and a second interconnect layer;
bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array using a bonding layer, such that at least one of the peripheral devices of the peripheral circuitry is electrically connected with at least one of the memory cells of the memory array; and
forming deep-trench-isolations extending into the first substrate and the well of the peripheral device from a second side of the first substrate wherein the deep-trench-isolations contact the first interconnect layer between source regions of neighboring peripheral devices and drain regions of the neighboring peripheral devices, wherein the first and second sides are opposite sides of the first substrate, and the deep-trench-isolations are configured to provide electrical isolation between at least two of the neighboring peripheral devices.