| CPC H01L 23/66 (2013.01) [H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/64 (2013.01); H01L 24/32 (2013.01); H01L 25/105 (2013.01); H01L 2223/6638 (2013.01)] | 20 Claims |
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18. A semiconductor package-on-package comprising:
a first semiconductor package comprising:
a lower redistribution layer comprising:
a surrounding equal potential plate comprising a differential signal opening;
a signal wiring layer in the differential signal opening;
a lower wiring layer comprising a lower equal potential plate, under the signal wiring layer;
a pair of differential signal wiring lines in the signal wiring layer, the pair of differential signal wiring lines comprising a first differential signal wiring line and a second differential signal wiring line, which extend spaced apart from each other; and
a lower redistribution insulating layer adjacent to the surrounding equal potential plate, the pair of differential signal wiring lines, and the lower equal potential plate;
an expanded layer overlapping portions of the pair of differential signal wiring lines in a vertical direction on the lower redistribution layer, the expanded layer comprising:
a substrate base comprising a mounting space;
a plurality of wiring patterns and an upper equal potential plate on at least one of a top surface of the substrate base and a bottom surface of the substrate base; and
a plurality of conductive vias passing through at least a portion of the substrate base,
an upper wiring layer in which the upper equal potential plate is provided above the signal wiring layer;
a first semiconductor chip in the mounting space on the lower redistribution layer; and
an upper redistribution layer on the expanded layer and the first semiconductor chip, the upper redistribution layer comprising:
a plurality of upper redistribution line patterns;
a plurality of upper redistribution via patterns; and
an upper redistribution insulating layer adjacent to the plurality of upper redistribution line patterns and the plurality of upper redistribution via patterns; and
a second semiconductor package comprising:
a second semiconductor chip electrically connected to the first semiconductor chip through the pair of differential signal wiring lines; and
package connection terminals on to package connection pads to electrically connect the second semiconductor chip to the first semiconductor package,
wherein the second semiconductor package is on the first semiconductor package, and
wherein the package connection pads are portions of the plurality of upper redistribution via patterns,
wherein the lower equal potential plate and the upper equal potential plate respectively have a lower impedance opening and an upper impedance opening which overlap at least portions of the pair of differential signal wiring lines in the vertical direction,
wherein the lower redistribution layer further comprises a lower equal potential bridge extending to bisect the lower impedance opening, the lower equal potential bridge being integrally formed with the lower equal potential plate,
wherein the expanded layer further comprises an upper equal potential bridge extending to bisect the upper impedance opening, the upper equal potential bridge being integrally formed with the upper equal potential plate, and
wherein the lower equal potential bridge and the upper equal potential bridge overlap a space between the first differential signal wiring line and the second differential signal wiring line in the vertical direction.
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