US 12,255,155 B2
Package structure with stacked semiconductor dies
Yi-Chao Mao, Zhongli (TW); Chin-Chuan Chang, Zhudong Township (TW); and Szu-Wei Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/587,290.
Application 17/587,290 is a continuation of application No. 16/227,449, filed on Dec. 20, 2018, granted, now 11,239,180.
Claims priority of provisional application 62/711,929, filed on Jul. 30, 2018.
Prior Publication US 2022/0157743 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/76816 (2013.01); H01L 24/08 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 2224/02333 (2013.01); H01L 2224/83203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a lower semiconductor die;
a first protective layer surrounding the lower semiconductor die;
a dielectric layer partially covering the first protective layer and the lower semiconductor die;
an upper semiconductor die over the lower semiconductor die and the first protective layer, wherein the upper semiconductor die is bonded with the lower semiconductor die through a connector;
an insulating film surrounding the connector; and
a second protective layer surrounding the upper semiconductor die, wherein a portion of the second protective layer is between the insulating film and the dielectric layer.