| CPC H01L 23/562 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |

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1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a memory array region in which each layer within the alternating stack is present and a staircase region in which lateral extents of the electrically conductive layers decrease as a function of a vertical distance from the substrate;
memory openings vertically extending through the alternating stack in the memory array region and each having a first lateral dimension;
memory opening fill structures located within a respective one of the memory openings, wherein the memory opening fill structures are arranged in a first hexagonal array having a nearest-neighbor direction that is parallel to a first horizontal direction and having a first nearest neighbor pitch a;
support openings vertically extending through the alternating stack in the staircase region and each having a second lateral dimension that is different from the first lateral dimension; and
support pillar structures located within a respective one of the support openings, wherein the support pillar structures are arranged in a second hexagonal array having a nearest-neighbor direction that is perpendicular to the first horizontal direction and having a second nearest neighbor pitch sa, in which s is a scaling factor having a value in a range from 1.25 to 1.7.
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