US 12,255,150 B2
CMP safe alignment mark
Huang-Jen Hsu, Hsinchu (TW); Jheng-Si Su, Hsinchu (TW); Kung-Ming Liu, Hsinchu (TW); Tzuyi Hsieh, Hsinchu (TW); and Feng-Inn Wu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 7, 2021, as Appl. No. 17/369,841.
Claims priority of provisional application 63/085,548, filed on Sep. 30, 2020.
Prior Publication US 2022/0102285 A1, Mar. 31, 2022
Int. Cl. H01L 23/544 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 29/06 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/02118 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/31053 (2013.01); H01L 29/0649 (2013.01); H01L 2223/54426 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a recess in a first region of a first surface of a wafer, the first region designated for an alignment mark, the recess extending in and downwardly beyond a first layer on a substrate of the wafer;
forming a device structure in a second region of the first surface of the wafer, the device structure extending in the first layer;
depositing a second layer on the first surface of the wafer, the second layer filling in the recess and at least laterally adjacent to the device structure;
conducting a first planarization procedure to remove a first portion of the second layer adjacent to the recess to a first level, with the device structure remaining in the first layer;
after the first planarization procedure, treating the second layer with oxygen plasma; and
after the treating the second layer with oxygen plasma, conducting a second planarization procedure to remove the device structure to a second level on the first layer.