US 12,255,143 B2
Microelectronic devices including composite pad structures on staircase structures, and related methods, memory devices, and electronic systems
Alyssa N. Scarbrough, Boise, ID (US); Jordan D. Greenlee, Boise, ID (US); and John D. Hopkins, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 26, 2021, as Appl. No. 17/187,481.
Prior Publication US 2022/0278051 A1, Sep. 1, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/53209 (2013.01) [H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 25 Claims
OG exemplary drawing
 
20. A memory device, comprising:
a stack structure comprising vertically alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising at least one of the conductive structures and at least one of the insulative structures;
a staircase structure having steps comprising edges of at least some of the tiers of the stack structure;
composite pad structures on the steps of the staircase structure and in direct physical contact with the insulative structures of the tiers of the stack structure at the steps of the staircase structure, each of the composite pad structures comprising:
a lower pad structure on one of the steps of the staircase structure, the lower pad structure comprising conductive material; and
an upper pad structure over the lower pad structure and at a same step of the staircase structure, the upper pad structure having a different material composition than that lower pad structure and having a larger horizontal dimension than the lower pad structure, at least one of horizontal ends of a relatively vertically higher upper pad structure substantially aligned with at least one of horizontal end of a relatively vertically lower upper pad structure horizontally neighboring the relatively vertically higher upper pad structure;
conductive contact structures vertically extending through the composite pad structures and to portions of at least some of the conductive structures of the stack structure at the steps of the staircase structure;
digit line structures overlying the stack structure;
a source structure underlying the stack structure;
an array of vertically extending strings of memory cells extending through the stack structure and coupled to the source structure and the digit line structures;
access line routing structures coupled to the conductive contact structures; and
a control logic circuitry vertically underlying the source structure and within horizontal boundaries of the array of vertically extending strings of memory cells, the control logic circuitry coupled to the source structure, the digit line structures, and the access line routing structures.