US 12,255,141 B2
Semiconductor integrated circuit device
Hideyuki Komuro, Yokohama (JP); and Junji Iwahori, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Jan. 11, 2024, as Appl. No. 18/410,874.
Application 18/410,874 is a continuation of application No. 17/322,570, filed on May 17, 2021, granted, now 11,908,799.
Application 17/322,570 is a continuation of application No. PCT/JP2019/044574, filed on Nov. 13, 2019.
Claims priority of application No. 2018-220392 (JP), filed on Nov. 26, 2018.
Prior Publication US 2024/0145390 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 23/535 (2013.01); H01L 27/092 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device including a standard cell as a capacitance cell, the standard cell comprising:
a first power supply line extending in a first direction and supplying a first power supply voltage,
a second power supply line extending in the first direction and supplying a second power supply voltage different from the first power supply voltage,
a first transistor that is a three-dimensional transistor of a first conductivity type,
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in a depth direction,
a third transistor that is a three-dimensional transistor of the first conductivity type, formed on a level with the first transistor in the depth direction, and
a fourth transistor that is a three-dimensional transistor of the second conductivity type, formed on a level with the second transistor in the depth direction,
a source and a drain of the first transistor and a source of the third transistor are connected to the first power supply line,
gates of the first, second, third and fourth transistors are mutually connected,
the second power supply voltage is supplied to the gates of the first, second, third and fourth transistors, and
the source of the third transistor is used in common with the source or drain of the first transistor, and the source of the fourth transistor is used in common with the source or drain of the second transistor.