| CPC H01L 23/5226 (2013.01) [H01L 21/76807 (2013.01); H01L 23/528 (2013.01); C04B 2235/61 (2013.01); G01V 2210/6242 (2013.01)] | 20 Claims |

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1. A method of forming an interconnect structure, comprising:
depositing a first etching stop layer over a substrate;
depositing a first dielectric layer over the first etching stop layer;
depositing a second etching stop layer over the first dielectric layer;
depositing an insert layer and a second dielectric layer over the second etching stop layer;
patterning the second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer, thereby forming a trench opening in the second dielectric layer and the insert layer, a via hole in the second etching stop layer, the first dielectric layer and the first etching stop layer, and a stack on the second etching stop layer and laterally beside the trench opening, wherein the stack has an aspect ratio greater than 2; and
filling a conductive feature in the trench opening and the via hole, thereby forming a conductive line in the second dielectric layer and the insert layer, and a via in the first etching stop layer and the first dielectric layer,
wherein a material of the insert layer is different from materials of the second dielectric layer and the second etch stop layer.
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