US 12,255,137 B2
Sideways vias in isolation areas to contact interior layers in stacked devices
Ehren Mannebach, Beaverton, OR (US); Aaron Lilak, Beaverton, OR (US); Hui Jae Yoo, Portland, OR (US); Patrick Morrow, Portland, OR (US); Anh Phan, Beaverton, OR (US); Willy Rachmady, Beaverton, OR (US); Cheng-Ying Huang, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); and Rishabh Mehandru, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 22, 2024, as Appl. No. 18/419,015.
Application 18/419,015 is a division of application No. 16/457,669, filed on Jun. 28, 2019, granted, now 11,942,416.
Prior Publication US 2024/0162141 A1, May 16, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/8234 (2006.01); H01L 25/16 (2023.01); H01L 29/06 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 25/16 (2013.01); H01L 29/0653 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first stack, wherein the first stack comprises:
a plurality of first components; and
a first plurality of insulating layers, wherein the plurality of first components are electrically isolated from each other by the first plurality of insulating layers;
an isolation region adjacent to the first stack, wherein the isolation region comprises:
a first wall that contacts a sidewall of the first stack;
a second wall that is parallel to the first wall; and
a fill layer between the first wall and the second wall; and
a via, wherein the via comprises:
a first portion between the first wall and the second wall that extends in a vertical direction; and
a second portion that extends away from the first portion, wherein the second portion passes through the first wall and contacts one of the plurality of first components.