| CPC H01L 23/5226 (2013.01) [H10B 43/27 (2023.02)] | 21 Claims |

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1. A semiconductor memory device, comprising:
a first conductive pattern including a first line component and a first pad component extending from the first line component;
a second conductive pattern overlapping the first line component of the first conductive pattern and leaving the first pad component of the first conductive pattern exposed, the second conductive pattern spaced apart from the first conductive pattern in a first direction;
an interlayer insulating layer between the first conductive pattern and the second conductive pattern;
a first conductive contact extending from the first pad component of the first conductive pattern in the first direction; and
a first insulating pillar overlapped by the first conductive contact and extending from the first pad component in a direction opposite to the first direction,
wherein the first insulating pillar includes a top surface facing the first conductive contact,
wherein the first pad component and the first line component form one body, and
wherein the first pad component completely covers the top surface of the first insulating pillar.
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