US 12,255,131 B2
Capacitor between two passivation layers with different etching rates
Chia-Ming Huang, Tainan (TW); Ming-Da Cheng, Taoyuan (TW); Songbor Lee, Zhubei (TW); Jung-You Chen, Zhubei (TW); Ching-Hua Kuan, Kaohsiung (TW); and Tzy-Kuang Lee, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 3, 2023, as Appl. No. 18/365,009.
Application 18/365,009 is a division of application No. 17/197,483, filed on Mar. 10, 2021, granted, now 11,935,826.
Claims priority of provisional application 63/030,597, filed on May 27, 2020.
Prior Publication US 2023/0378052 A1, Nov. 23, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/5223 (2013.01) [H01L 23/5226 (2013.01); H01L 24/03 (2013.01); H01L 28/60 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a metal pad;
a first etch stop layer over the metal pad;
a first passivation layer over and contacting the first etch stop layer;
a capacitor over the first passivation layer, the capacitor comprising a capacitor electrode and a capacitor insulator over and contacting the capacitor electrode;
a second passivation layer over the first passivation layer, wherein the first passivation layer is more porous than the second passivation layer;
a first redistribution line comprising:
a first via extending from a top surface of the second passivation layer to a first top surface of the metal pad; and
a first metal line over and joined to the first via; and
a second redistribution line comprising:
a second via extending from the top surface of the second passivation layer to a second top surface of the capacitor electrode; and
a second metal line over and joined to the second via.