US 12,255,129 B2
Signal routing in integrated circuit packaging
Jin Young Kim, Mountain View, CA (US); and Zhonghua Wu, Fremont, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Oct. 3, 2023, as Appl. No. 18/480,292.
Application 18/480,292 is a continuation of application No. 17/684,218, filed on Mar. 1, 2022, granted, now 11,810,850.
Application 17/684,218 is a continuation of application No. 16/910,244, filed on Jun. 24, 2020, granted, now 11,302,624, issued on Apr. 12, 2022.
Application 16/910,244 is a continuation of application No. 16/474,687, granted, now 10,734,319, issued on Aug. 4, 2020, previously published as PCT/US2018/053848, filed on Oct. 2, 2018.
Claims priority of provisional application 62/569,063, filed on Oct. 6, 2017.
Prior Publication US 2024/0105581 A1, Mar. 28, 2024
Int. Cl. H01L 23/50 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/50 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A substrate configured to couple with an integrated circuit, the substrate comprising:
a first layer comprising a region having one or more signal traces, the first layer having first ground stripes placed adjacent to the one or more signal traces along opposite sides of one or more signal traces; and
a second layer located above or below the first layer, wherein the second layer has one or more power stripes and one or more second ground stripes arranged so that the one or more second ground stripes are aligned with the one or more signal traces of the first layer.