US 12,255,125 B2
Semiconductor structure and manufacturing method thereof
Chih-Cheng Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 27, 2022, as Appl. No. 17/649,099.
Application 17/649,099 is a continuation of application No. PCT/CN2021/112007, filed on Aug. 11, 2021.
Claims priority of application No. 202110898158.5 (CN), filed on Aug. 5, 2021.
Prior Publication US 2023/0044396 A1, Feb. 9, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53271 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate and a via located in the substrate;
a conductive pillar located in the via, wherein the conductive pillar is provided with a groove extending inwards from an upper surface of the conductive pillar; and
a core layer located in the groove, wherein a Young modulus of the core layer is less than a Young modulus of the conductive pillar;
wherein the semiconductor structure further comprises at least one buffer layer located between the substrate and the conductive pillar, and a Young modulus of the buffer layer is less than a Young modulus of the substrate.