US 12,255,114 B2
Embedded package with electrically isolating dielectric liner
Eung San Cho, Torrance, CA (US)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Dec. 20, 2023, as Appl. No. 18/390,603.
Application 18/390,603 is a division of application No. 17/511,787, filed on Oct. 27, 2021, granted, now 11,881,437.
Prior Publication US 2024/0120248 A1, Apr. 11, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/3135 (2013.01) [H01L 23/3121 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/221 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor package, the method comprising:
producing a package substrate that comprises an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer;
providing a first semiconductor die with a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die that is opposite from the first surface of the first semiconductor die; and
providing a liner of dielectric material on the first semiconductor die;
embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and
wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.