US 12,255,111 B2
Multiple-level interconnect structure and manufacturing method thereof
Jia Fang Wu, Chiayi (TW); Hsiang-Chieh Yen, Penghu County (TW); Hsu-Sheng Huang, Kaohsiung (TW); and Zhi Jian Wang, Tainan (TW)
Assigned to United Microelectronics Corp., Hsinchu (TW)
Filed by United Microelectronics Corp., Hsinchu (TW)
Filed on Aug. 4, 2021, as Appl. No. 17/394,197.
Claims priority of application No. 202110726462.1 (CN), filed on Jun. 29, 2021.
Prior Publication US 2022/0415724 A1, Dec. 29, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 23/522 (2006.01)
CPC H01L 22/30 (2013.01) [H01L 22/12 (2013.01); H01L 23/5226 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A multi-level interconnect structure, having a scatterometry test layer, comprising:
a patterned reflective layer, disposed on a substrate and comprising a first reflective pattern and a second reflective pattern separated from each other;
a bulk reflective layer, disposed directly on the patterned reflective layer; and
a patterned test layer, disposed over the bulk reflective layer,
wherein from a top view of the substrate, a ratio of a projected area of the patterned reflective layer to a projected area of the bulk reflective layer is between 0.75 and 0.90, and
wherein the first reflective pattern comprises a plurality of first conductive via patterns, the second reflective pattern comprises a plurality of second conductive via patterns, the first conductive via patterns and the second conductive via patterns are arranged in an array, and the first conductive via patterns with a smaller aperture are located between adjacent second conductive via patterns with a larger aperture.