US 12,255,106 B2
Multi-Vt nanosheet devices
Jingyun Zhang, Albany, NY (US); Takashi Ando, Eastchester, NY (US); ChoongHyun Lee, Chigasaki (JP); and Alexander Reznicek, Troy, NY (US)
Assigned to INTERATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Nov. 16, 2021, as Appl. No. 17/527,355.
Prior Publication US 2023/0154798 A1, May 18, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/823462 (2013.01) [H01L 21/823412 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels, the method comprising:
forming a first set of nanosheet stacks having a first intersheet spacing;
forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing;
depositing a high-k (HK) layer within the first and second nanosheet stacks;
depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks;
depositing a dipole material; and
selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.