US 12,255,105 B2
Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same
Pei-Hsun Wu, Hsinchu (TW); Ming-Hung Han, Hsinchu (TW); Po-Nien Chen, Miaoli County (TW); and Chih-Yung Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jun. 30, 2021, as Appl. No. 17/363,837.
Application 17/363,837 is a continuation of application No. 16/728,154, filed on Dec. 27, 2019, granted, now 11,056,396.
Prior Publication US 2021/0327765 A1, Oct. 21, 2021
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823462 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7854 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first transistor located in the first region, the first transistor including:
a first channel layer suspended above the substrate;
a first gate dielectric layer fully wrapping around the first channel layer, the first gate dielectric layer having a first thickness; and
a first gate structure on the first gate dielectric layer;
a second transistor located in the first region, the second transistor including:
a second channel layer suspended above the substrate;
a second gate dielectric layer fully wrapping around the second channel layer, the second gate dielectric layer having a second thickness, the second thickness being greater than the first thickness; and
a second gate structure on the second gate dielectric layer; and
a third transistor located in the second region, the third transistor including:
a third channel layer suspended above the substrate;
a third gate dielectric layer fully wrapping around the third channel layer, the third gate dielectric layer having a third thickness, the third thickness being greater than the second thickness; and
a third gate structure on the third gate dielectric layer,
wherein the first gate dielectric layer includes a first interfacial layer and a first high-k dielectric layer, the second gate dielectric layer includes a second interfacial layer and a second high-k dielectric layer, the third gate dielectric layer includes a third interfacial layer and a third high-k dielectric layer, and wherein the first interfacial layer is thinner than the second interfacial layer, and the second interfacial layer is thinner than the third interfacial layer,
wherein the first gate dielectric layer further includes a metal silicate layer interposing the first interfacial layer and the first high-k dielectric layer, and wherein in the second gate dielectric layer the second interfacial layer is in physical contact with the second high-k dielectric layer.