US 12,255,104 B2
Semiconductor device and method of manufacture
Chia-Ching Lee, New Taipei (TW); Hsin-Han Tsai, Hsinchu (TW); Shih-Hang Chiu, Taichung (TW); Tsung-Ta Tang, Hsinchu (TW); Chung-Chiang Wu, Taichung (TW); Hung-Chin Chung, Pingzhen (TW); Hsien-Ming Lee, Changhua (TW); Da-Yuan Lee, Jhubei (TW); Jian-Hao Chen, Hsinchu (TW); Chien-Hao Chen, Chuangwei Township (TW); Kuo-Feng Yu, Zhudong Township (TW); Chia-Wei Chen, Hsinchu (TW); and Chih-Yu Hsu, Xinfeng Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/363,945.
Application 18/363,945 is a division of application No. 17/870,343, filed on Jul. 21, 2022, granted, now 12,040,235.
Application 17/870,343 is a division of application No. 16/900,439, filed on Jun. 12, 2020, granted, now 11,437,280, issued on Sep. 6, 2022.
Prior Publication US 2023/0386926 A1, Nov. 30, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/82345 (2013.01) [H01L 27/0886 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first transistor channel;
a first gate spacer and second gate spacer; and
a first gate stack comprising a set of liner layers, the set of liner layers sequentially including a gate dielectric layer, a barrier layer over the gate dielectric layer, a first work function layer over the barrier layer, a first anti-reaction layer over the first work function layer, and a conductive fill disposed over the first anti-reaction layer, wherein the gate dielectric layer is disposed on the first gate spacer, the second gate spacer, and the first transistor channel, and wherein the first anti-reaction layer comprises a multi-layer structure comprising at least two different material layers.