US 12,255,103 B2
Semiconductor structure with backside via contact and a protection liner layer
Li-Zhen Yu, New Taipei (TW); Chia-Hao Chang, Hsinchu (TW); Huan-Chieh Su, Changhua County (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Yu-Ming Lin, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/354,323.
Application 18/354,323 is a division of application No. 17/231,493, filed on Apr. 15, 2021, granted, now 11,710,664.
Prior Publication US 2023/0369119 A1, Nov. 16, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/76224 (2013.01); H01L 29/6681 (2013.01); H01L 29/7827 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit structure, comprising:
receiving a substrate having a front side and a back side opposite to the front side;
forming a shallow trench in the substrate from the front side;
forming a liner layer including a first dielectric material in the shallow trench;
depositing a second dielectric material on the liner layer to form an isolation feature in the shallow trench, wherein the second dielectric material is different from the first dielectric material;
forming an active region surrounded by the isolation feature;
forming a gate stack on the active region;
forming a source/drain (S/D) feature on the active region and on a side of the gate stack;
thinning down the substrate from the back side such that the isolation feature is exposed;
etching the active region to expose the S/D feature from the back side to form a backside trench; and
forming a backside via feature landing on the S/D feature and surrounded by the liner layer.