US 12,255,100 B2
Inner filler layer for multi-patterned metal gate for nanostructure transistor
Shahaji B. More, Hsinchu (TW); and Chandrashekhar Prakash Savant, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,717.
Application 18/361,717 is a continuation of application No. 17/316,486, filed on May 10, 2021, granted, now 11,749,566.
Claims priority of provisional application 63/138,270, filed on Jan. 15, 2021.
Prior Publication US 2023/0377977 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823412 (2013.01) [H01L 21/0259 (2013.01); H01L 21/02603 (2013.01); H01L 21/31111 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
15. An integrated circuit, comprising:
a first nanostructure transistor including a plurality of first semiconductor nanostructures;
a second nanostructure transistor including a plurality of second semiconductor nanostructures;
a third nanostructure transistor including a plurality of third semiconductor nanostructures;
an inter sheet filler layer between the second semiconductor nanostructures;
a first gate metal layer substantially filling a space between the first semiconductor nanostructures and in contact with the inter-sheet filler layer; and
a second gate metal layer substantially filling a space between the third semiconductor nanostructures.