CPC H01L 21/8221 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0688 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] | 19 Claims |
1. A method of forming a plurality of transistor stacks, the method comprising:
providing a stack comprising a plurality of nanosheets and a semiconductor layer that is on the nanosheets;
forming a mask on the stack, wherein the semiconductor layer is between the mask and the nanosheets;
forming an asymmetric layer on the mask, the asymmetric layer comprising a plurality of segments, at least some of which have different respective widths;
forming first spacers on sidewalls of the segments of the asymmetric layer;
etching the mask, while the first spacers are thereon, to form a plurality of mask segments between the first spacers, respectively, and the semiconductor layer;
etching the semiconductor layer to form a plurality of fins between the mask segments, respectively, and the nanosheets;
forming second spacers on sidewalls of the fins; and
etching the nanosheets, while the second spacers are on the sidewalls of the fins, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the fins thereon with a corresponding fin sidewall that is coplanar with a sidewall of an underlying one of the plurality of spaced-apart nanosheet stacks.
|