US 12,255,096 B2
Semiconductor device with reduced contact resistance and methods of forming the same
Kuo-Chiang Tsai, Hsinchu (TW); and Jhy-Huei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,592.
Application 17/588,547 is a division of application No. 16/571,358, filed on Sep. 16, 2019, granted, now 11,239,114, issued on Feb. 1, 2022.
Application 18/361,592 is a continuation of application No. 17/588,547, filed on Jan. 31, 2022, granted, now 11,728,216.
Prior Publication US 2023/0377965 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76847 (2013.01); H01L 23/5226 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first gate stack disposed over a substrate, the first gate stack including a gate dielectric layer and a gate electrode layer;
a first sidewall spacer disposed along a first sidewall of the first gate stack;
a first metal layer disposed directly on the gate electrode layer and the gate dielectric layer, wherein the first sidewall spacer extends to a first height above the substrate and the first metal layer extends to a second height above the substrate, the second height being less than the first height; and
a first contact feature extending to the first metal layer positioned at the second height above the substrate.