US 12,255,095 B2
Semiconductor structure and manufacturing method thereof
Yu-Kai Lin, Changhua County (TW); Su-Jen Sung, Hsinchu County (TW); Tze-Liang Lee, Hsinchu (TW); and Jen-Hung Wang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 1, 2023, as Appl. No. 18/310,527.
Application 18/310,527 is a continuation of application No. 17/192,805, filed on Mar. 4, 2021, granted, now 11,670,546.
Prior Publication US 2023/0274975 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76832 (2013.01) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76826 (2013.01); H01L 21/76828 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A semiconductor structure, comprising:
a substrate; and
an interconnect structure disposed over the substrate, the interconnect structure comprising interlayer dielectric layers, an etch stop layer between two of the interlayer dielectric layers and conductive features embedded in the interlayer dielectric layers, wherein the etch stop layer comprises an insulating layer comprising a metal oxide region covering at least one of the interlayer dielectric layers and at least one metal nitride region covering the conductive features, and one of the conductive features penetrates the at least one metal nitride region.