CPC H01L 21/76816 (2013.01) [H01L 23/5283 (2013.01); H10B 41/30 (2023.02); H10B 41/50 (2023.02); H10B 43/50 (2023.02)] | 17 Claims |
1. A 3D memory structure, comprising:
a substrate comprising a memory cell region and a peripheral region surrounding the memory cell region;
an etching stop layer disposed on the substrate;
a 3D memory array disposed on the etching stop layer on the memory cell region, wherein the 3D memory array comprises a first stacked structure comprising gate layers stacked on each other and electrically isolated from each other; and
a second stacked structure disposed on the etching stop layer and surrounding the first stacked structure of the 3D memory array, wherein the second stacked structure comprises dummy gate layers stacked on each other and electrically isolated from each other,
wherein the first stacked structure comprises first sidewalls that face the second stacked structure, the second stacked structure comprises second sidewalls that face the first stacked structure, the first sidewalls define an inner sidewall of a trench pattern, and the second sidewalls define an outer sidewall of the trench pattern,
wherein the inner sidewall and the outer sidewall of the trench pattern are asymmetric, wherein the outer sidewall comprises a curve profile, and the inner sidewall comprises a staircase profile.
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