| CPC H01L 21/68757 (2013.01) [H01L 21/67167 (2013.01); H01L 21/67173 (2013.01); H01L 21/6719 (2013.01); H01L 21/67196 (2013.01); H01L 21/67201 (2013.01); H01L 21/67242 (2013.01); H01L 21/67742 (2013.01); H01L 22/10 (2013.01); H05F 1/00 (2013.01)] | 20 Claims |

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1. A semiconductor processing apparatus, comprising:
a wafer handling structure, the wafer handling structure configured to support a semiconductor wafer during processing of the semiconductor wafer in the semiconductor processing apparatus; and
an electrostatic discharge (ESD) prevention layer on the wafer handling structure, the ESD prevention layer including a first material and a second material, the second material having an electrical conductivity that is greater than an electrical conductivity of the first material,
wherein the ESD prevention layer includes a homogeneous mixture of the first material and the second material, and wherein the ESD prevention layer further includes at least one additive material, the at least one additive material including at least one of an anti-acid material, an anti-base material, or an anti-extreme ultraviolet (EUV) material.
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