US 12,255,065 B2
Semiconductor devices including a support pattern on a lower electrode structure
Hyun-Suk Lee, Suwon-si (KR); Jungoo Kang, Seoul (KR); Gihee Cho, Yongin-si (KR); and Sanghyuck Ahn, Daegu (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 5, 2023, as Appl. No. 18/529,024.
Application 18/529,024 is a continuation of application No. 17/851,244, filed on Jun. 28, 2022, granted, now 11,875,992.
Application 17/851,244 is a continuation of application No. 16/853,796, filed on Apr. 21, 2020, granted, now 11,404,266, issued on Aug. 2, 2022.
Claims priority of application No. 10-2019-0106808 (KR), filed on Aug. 29, 2019.
Prior Publication US 2024/0120196 A1, Apr. 11, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/12 (2006.01); H01L 21/302 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/0228 (2013.01) [H01L 21/12 (2013.01); H01L 21/302 (2013.01); H01L 21/76885 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate;
forming lower electrode pillars filling the electrode holes;
etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer;
forming metal residual patterns on a surface of the support pattern;
removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and
selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars,
wherein the metal residual patterns are spaced apart from the lower electrode patterns.