| CPC G11C 7/1066 (2013.01) [G11C 7/222 (2013.01); H03L 7/0995 (2013.01); G11C 2207/2254 (2013.01)] | 20 Claims |
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1. A method implemented by a multi-chip package (MCP) electronic device including a die-to-die (D2D) interface, the method comprising:
receiving, by a receiver portion of a first die of the D2D interface, and from a transmitter portion of a second die of the D2D interface, a first timing signal and a second timing signal;
generating a timing calibration signal based on a timing value corresponding substantially to a midpoint of an estimated margin between overlaying segments of the first timing signal and a timing value corresponding to a delay of a unit delay associated with the receiver portion;
generating an output timing signal based on the timing calibration signal; and
selecting a timing delay signal based on the output timing signal and the timing calibration signal, the timing delay signal being selected to reduce a potential glitch power associated with the receiver portion.
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