US 12,254,948 B2
Standby exit for memory die stack
Hari Giduturi, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 19, 2022, as Appl. No. 17/723,798.
Prior Publication US 2023/0335165 A1, Oct. 19, 2023
Int. Cl. G11C 5/06 (2006.01); G11C 5/14 (2006.01); H01L 25/065 (2023.01)
CPC G11C 5/148 (2013.01) [G11C 5/063 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method comprising:
idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), wherein the first memory device comprises a primary die coupled to multiple secondary dies using an intra-package bus, and wherein the first memory device communicates with the host exclusively via the primary die and an inter-device bus; and
at the first memory device:
waking logic circuitry on the primary die in response to a state change on the standby exit line; and
sampling the command line using the logic circuitry on the primary die, and when a wakeup message on the command line comprises a chip identification that corresponds to a secondary die of the first memory device, initiating a standby exit procedure for the secondary die of the first memory device.