| CPC G11C 29/808 (2013.01) [G11C 29/52 (2013.01); G11C 29/802 (2013.01)] | 20 Claims |
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1. A neuromorphic device comprising:
a first memory cell array comprising:
first resistive memory cells connected to word lines, bit lines, and source lines,
second resistive memory cells connected to the word lines, at least one redundancy bit line, and at least one redundancy source line, and
third resistive memory cells connected to at least one redundancy word line, the bit lines, and the source lines,
wherein the first memory cell array is configured to store weight data corresponding to a weight of a neural network in the first resistive memory cells, and generate a plurality of read currents based on input signals and the weight data;
a second memory cell array comprising:
first reference resistive memory cells connected to reference word lines, reference bit lines, and reference source lines,
second reference resistive memory cells connected to the reference word lines, at least one redundancy reference bit line, and at least one redundancy reference source line,
third reference resistive memory cells connected to at least one redundancy reference word line, the reference bit lines, and the reference source lines,
wherein the second memory cell array is configured to generate a plurality of reference currents; and
an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals based on the plurality of reference currents.
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