US 12,254,944 B2
Test system and test method for dynamic random access memory module of intel system
Wei-Guo Zhao, Shanghai (CN)
Assigned to SQ TECHNOLOGY (SHANGHAI) CORPORATION, Shanghai (CN); and INVENTEC CORPORATION, Taipei (TW)
Filed by SQ TECHNOLOGY (SHANGHAI) CORPORATION, Shanghai (CN); and INVENTEC CORPORATION, Taipei (TW)
Filed on Jun. 19, 2023, as Appl. No. 18/211,496.
Claims priority of application No. 202310556163.7 (CN), filed on May 17, 2023.
Prior Publication US 2024/0386986 A1, Nov. 21, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 29/04 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/56 (2013.01) [G11C 29/04 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A test system for a DRAM module of an INTEL system, configured to verify information write and read functions of an EEPROM comprised the DRAM module, wherein the test system comprises:
at least one memory module slot configured for insertion of the DRAM module;
a processing unit comprising a plurality of operation registers, one of the plurality of operation registers further comprising a central processing unit bus register, wherein the central processing unit bus register is electrically coupled to at least one system management bus and configured for accessing the at least one memory module slot connected to the at least one system management bus according to a bus identifier corresponding to the at least one system management bus;
wherein the operation register comprising the central processing unit bus register accesses the DRAM module through the at least one system management bus, and writes test data to and reads the test data from the EEPROM.