US 12,254,943 B2
Signal detection system for duty cycle testing and memory detection method
Jianyong Qin, Hefei (CN); Jianni Li, Hefei (CN); and Zhonglai Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 29, 2022, as Appl. No. 17/955,670.
Application 17/955,670 is a continuation of application No. PCT/CN2022/093714, filed on May 19, 2022.
Claims priority of application No. 202210450141.8 (CN), filed on Apr. 26, 2022.
Prior Publication US 2023/0012586 A1, Jan. 19, 2023
Int. Cl. G11C 29/50 (2006.01); G11C 7/22 (2006.01); H03K 5/156 (2006.01); H03K 3/03 (2006.01)
CPC G11C 29/50012 (2013.01) [G11C 7/222 (2013.01); H03K 5/1565 (2013.01); H03K 3/0315 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal detection system, applied to a memory, configured to perform a duty cycle test on output signals of test paths in the memory according to a test circuit in the memory, and comprising:
a signal generator, configured to generate a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, wherein
the duty cycle test is performed on the reference test signal based on the test circuit, to determine whether a function of the test circuit is normal;
in response to determining that the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test; the portions under test comprise a signal conversion circuit and a write clock path; the signal conversion circuit is configured to generate an internal clock signal according to the reference test signal; and the write clock path comprises a write frequency divider, a write clock tree, and a signal loading circuit; and
the write frequency divider is configured to generate a parallel write clock according to the internal clock signal, the write clock tree is configured to adjust a delay of the parallel write clock, and the signal loading circuit is configured to sample preset data according to the parallel write clock, to generate a first indication signal and a second indication signal.