US 12,254,941 B2
Test circuit, test method and memory
Jianyong Qin, Hefei (CN); Jianni Li, Hefei (CN); and Zhonglai Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 29, 2022, as Appl. No. 17/955,658.
Application 17/955,658 is a continuation of application No. PCT/CN2022/093712, filed on May 19, 2022.
Claims priority of application No. 202210451906.X (CN), filed on Apr. 26, 2022.
Prior Publication US 2023/0021184 A1, Jan. 19, 2023
Int. Cl. G11C 29/46 (2006.01); G06F 1/04 (2006.01); G06F 13/16 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/46 (2013.01) [G06F 1/04 (2013.01); G06F 13/1689 (2013.01); G11C 29/12005 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A test circuit for testing a duty cycle of a signal, comprising:
a first integration circuit configured to receive a first test signal and integrate the first test signal to output a first integrated signal;
a second integration circuit configured to receive a second test signal and integrate the second test signal to output a second integrated signal,
wherein the first test signal and the second test signal are signals inverted with respect to each other, a voltage value of the first integrated signal is a product of a duty cycle of the first test signal and a voltage amplitude of a power supply, and a voltage value of the second integrated signal is a product of a duty cycle of the second test signal and the voltage amplitude of the power supply; and
a comparison circuit having one input terminal connected to the first integration circuit, and the other input terminal connected to the second integration circuit,
wherein the comparison circuit is configured to compare a voltage value of the first integrated signal and a voltage value of the second integrated signal, output a high-level signal in response to the first integrated signal being greater than the second integrated signal, and output a low-level signal in response to the second integrated signal being greater than the first integrated signal; and
wherein the test circuit further comprises; a control module configured to provide, based on a control enable signal, control signals required for duty cycle test by the first integration circuit, the second integration circuit and the comparison circuit.