| CPC G11C 29/4401 (2013.01) [G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/0766 (2013.01); G11C 29/76 (2013.01); G11C 2029/4402 (2013.01)] | 20 Claims |

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1. A method of operation of a memory controller which controls an operation of a memory device that includes a memory region and a repair memory region, the memory controller comprising a first error counter and a second error counter, the method comprising:
receiving an address associated with the memory region that is included in a first read command and data read out from the memory region associated with the address;
decoding the data using an error correction code and detecting an error included in the data;
generating error type information indicating a type of the error included in the data;
updating, based on the error type information, a count value of one of the first error counter and the second error counter associated with the address, the count value indicating a number of times that the type of error indicated by the error type information has occurred for the address;
comparing the count value with a threshold value, wherein the threshold value is one of a first threshold value and a second threshold value smaller than the first threshold value, wherein the first threshold value is associated with the first error counter, and wherein the second threshold value is associated with the second error counter; and
when the count value is equal to the threshold value, backing up the data that is stored in the memory region associated with the address to the repair memory region.
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