US 12,254,939 B2
Memory structure and memory device
Weibing Shang, Hefei (CN); and Hongwen Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/908,477
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed May 12, 2022, PCT No. PCT/CN2022/092551
§ 371(c)(1), (2) Date Aug. 31, 2022,
PCT Pub. No. WO2023/071144, PCT Pub. Date May 4, 2023.
Claims priority of application No. 202111270751.1 (CN), filed on Oct. 29, 2021.
Prior Publication US 2024/0194286 A1, Jun. 13, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/44 (2013.01) 14 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
a plurality of memory arrays arranged in parallel along a first direction and extending along a second direction,
wherein a sensitivity amplifier array extending along the second direction is arranged between every two of the plurality of memory arrays, wherein the sensitivity amplifier array comprises an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, wherein the odd-numbered sensitivity amplifier array and the even-numbered sensitivity amplifier array are alternating along a first direction, and wherein the odd-numbered sensitivity amplifier array is connected to a plurality of odd-numbered global signal lines, and the even-numbered sensitivity amplifier array is connected to a plurality of even-numbered global signal lines;
and
at least one spare memory array, arranged on at least one side of the plurality of memory arrays in the first direction, wherein a first sensitivity amplifier array is arranged between a spare memory array and a memory array at the edge, and wherein the first sensitivity amplifier array is connected to the odd-numbered memory array; and, wherein
wherein both the plurality of odd-numbered global signal lines and the plurality of even-numbered global signal lines are connected.