US 12,254,938 B2
Memory device with serial and parallel testing structure for sensing amplifiers
ALberto Troia, Munich (DE); and Antonino Mondello, Messina (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jun. 20, 2022, as Appl. No. 17/844,557.
Application 17/844,557 is a continuation of application No. 16/625,105, granted, now 11,367,497, previously published as PCT/IB2019/000475, filed on May 31, 2019.
Prior Publication US 2023/0410930 A1, Dec. 21, 2023
Int. Cl. G11C 29/32 (2006.01); G11C 29/02 (2006.01); G11C 29/06 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/32 (2013.01) [G11C 29/02 (2013.01); G11C 29/06 (2013.01); G11C 29/1201 (2013.01); G11C 29/42 (2013.01); G11C 2029/3202 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array including a plurality of sub-arrays of memory cells and structured in memory blocks, wherein:
each sub-array corresponds to a different core of a System-on-a Chip (SoC) structure;
each core is coupled to a different corresponding channel for receiving data at the memory device and transferring the data from the memory device;
the memory device includes sense amplifiers coupled to the memory cells;
the memory device includes modified JTAG cells coupled in parallel to outputs of the sense amplifiers and serially interconnected in a scan-chain structure that integrates a JTAG structure and the sense amplifiers with independent serial and parallel outputs; and
scan-chain structures associated to each sub-array are interconnected to form a unique chain as a boundary scan register.