US 12,254,937 B2
Semiconductor device and method for performing test
Choung Ki Song, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Jan. 12, 2023, as Appl. No. 18/096,407.
Claims priority of application No. 10-2022-0128187 (KR), filed on Oct. 6, 2022.
Prior Publication US 2024/0120015 A1, Apr. 11, 2024
Int. Cl. G11C 29/04 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01); G11C 29/14 (2006.01); G11C 29/18 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/14 (2013.01) [G11C 29/023 (2013.01); G11C 29/04 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/18 (2013.01); G11C 2029/0409 (2013.01); G11C 29/36 (2013.01); G11C 2207/2254 (2013.01)] 41 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal;
a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells of the semiconductor device based on the internal clock and the internal control signal; and
a data control circuit configured to output data stored in the first memory cells and to store the data output from the first memory cells in the second memory cells based on the test command.