US 12,254,933 B2
Smart prologue for nonvolatile memory program operation
Pranav Chava, Folsom, CA (US); Aliasgar S. Madraswala, Folsom, CA (US); Sagar Upadhyay, Folsom, CA (US); and Bhaskar Venkataramaiah, Folsom, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Apr. 30, 2024, as Appl. No. 18/651,261.
Application 18/651,261 is a division of application No. 16/895,890, filed on Jun. 8, 2020, granted, now 12,046,303.
Prior Publication US 2024/0290405 A1, Aug. 29, 2024
Int. Cl. G11C 16/12 (2006.01); G11C 7/22 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/222 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a nonvolatile (NV) storage media to be written by an operation to program a cell and then verify the cell program, the NV storage media including a block of storage with multiple subblocks, the cell being a single level cell (SLC);
a storage device to store a computed program parameter; and
a controller to compute a program parameter to program a first subblock of the multiple subblocks for a program prologue, apply the program parameter to program the first subblock, perform a program epilogue for the first subblock, store the program parameter in the storage device, and apply the program parameter from the storage device to program the other subblocks of the block without re-computation of the program parameter for the other subblocks, and skip program epilogue for the other subblocks until a last of the other subblocks.