US 12,254,932 B2
Memory device for effectively checking program state and operation method thereof
Soo Yeol Chai, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 2, 2022, as Appl. No. 18/073,751.
Claims priority of application No. 10-2022-0093789 (KR), filed on Jul. 28, 2022.
Prior Publication US 2024/0038312 A1, Feb. 1, 2024
Int. Cl. G11C 11/08 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of page buffers connected to a plurality of memory cells through a plurality of bit lines and configured to selectively precharge the bit lines; and
a control circuit configured to:
perform a first verify operation by applying a precharge voltage to at least one first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line,
perform a second verify operation, after the first verify operation, by applying the precharge voltage to at least one second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line,
perform an operation of floating the first bit line connected to the memory cell programmed with a threshold voltage higher than the second verify voltage, and
perform the operation of applying the precharge voltage to the first bit line connected to the memory cell programmed with the threshold voltage lower than the second verify voltage.