US 12,254,931 B2
Three-bit-per-cell programming using a four-bit-per-cell programming algorithm
Xiang Yang, Santa Clara, CA (US); Deepanshu Dutta, Fremont, CA (US); Jiacen Guo, Sunnyvale, CA (US); Takayuki Inoue, Sagamihara (JP); and Hua-Ling Hsu, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 21, 2022, as Appl. No. 17/845,060.
Prior Publication US 2023/0410921 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3454 (2013.01) [G11C 7/1039 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory cells;
logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells using a 4-bit gray code; and
a control circuit coupled to the memory cells and the logic circuits, the control circuit configured to cause the logic circuits to use the 4-bit gray code to store only 3-bit data in each of the memory cells using fewer than sixteen possible threshold voltages.