US 12,254,930 B2
Control method for memory erase operations, apparatus, and storage medium thereof
Junbao Wang, Wuhan (CN); and Jianquan Jia, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 15, 2022, as Appl. No. 18/082,491.
Application 18/082,491 is a continuation of application No. PCT/CN2021/129551, filed on Nov. 9, 2021.
Claims priority of application No. 202110011459.1 (CN), filed on Jan. 6, 2021.
Prior Publication US 2023/0121846 A1, Apr. 20, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A control method for a memory, wherein the memory comprises memory blocks each comprising memory strings, each of the memory strings comprises a channel layer with an N-type doped top region, and the control method comprises:
applying a bit line erasing voltage to a select bit line;
applying a top select gate voltage to a top select gate, wherein the top select gate voltage is lower than the bit line erasing voltage to form a potential difference, in the N-type doped top region, above the top select gate, and the bit line erasing voltage and the top select gate voltage change synchronously; and
applying a word line erasing voltage lower than the bit line erasing voltage to corresponding word lines of a memory string connected to the select bit line, to implement erasing of the memory string connected to the select bit line.