	US 12,254,929 B2
	Semiconductor memory device
Masanobu Shirakawa, Chigasaki Kanagawa (JP); Takuya Futatsuyama, Yokohama Kanagawa (JP); Kenichi Abe, Yokohama Kanagawa (JP); Hiroshi Nakamura, Fujisawa Kanagawa (JP); Keisuke Yonehama, Kamakura Kanagawa (JP); Atsuhiro Sato, Meguro Tokyo (JP); Hiroshi Shinohara, Yokosuka Kanawaga (JP); Yasuyuki Baba, Ayase Kanagawa (JP); and Toshifumi Minami, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on May 31, 2023, as Appl. No. 18/326,587.
Application 18/326,587 is a continuation of application No. 17/585,370, filed on Jan. 26, 2022, granted, now 11,705,204.
Application 17/585,370 is a continuation of application No. 17/103,504, filed on Nov. 24, 2020, granted, now 11,270,773, issued on Mar. 8, 2022.
Application 17/103,504 is a continuation of application No. 16/459,495, filed on Jul. 1, 2019, granted, now 10,854,298, issued on Dec. 1, 2020.
Application 16/459,495 is a continuation of application No. 16/056,835, filed on Aug. 7, 2018, granted, now 10,381,084, issued on Aug. 13, 2019.
Application 16/056,835 is a continuation of application No. 15/791,178, filed on Oct. 23, 2017, granted, now 10,074,434, issued on Sep. 11, 2018.
Application 15/791,178 is a continuation of application No. 15/174,849, filed on Jun. 6, 2016, granted, now 9,799,403, issued on Oct. 24, 2017.
Application 15/174,849 is a continuation of application No. 14/469,522, filed on Aug. 26, 2014, granted, now 9,361,988, issued on Jun. 7, 2016.
Claims priority of application No. 2014-052746 (JP), filed on Mar. 14, 2014.
Prior Publication US 2023/0317173 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/00 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 29/42 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); G11C 16/34 (2006.01)

CPC G11C 16/14 (2013.01) [G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/42 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02); G11C 16/3445 (2013.01)]

16 Claims

1. A semiconductor memory device comprising:

a source line;

a bit line;

a memory cell array including a memory string electrically connected between the bit line and the source line, the memory string including a first select transistor, a second select transistor, and a plurality of memory cell transistors electrically connected in series between the first select transistor and the second select transistor, the memory cell transistors including

a first memory cell transistor,

a second memory cell transistor, wherein the first memory cell transistor is between the first select transistor and the second memory cell transistor,

a third memory cell transistor, and

a fourth memory cell transistor, wherein the fourth memory cell transistor is between the third memory cell transistor and the second select transistor;

a plurality of word lines electrically connected to gates of the memory cell transistors, respectively, the word lines including

a first word line electrically connected to the gate of the first memory cell transistor,

a second word line electrically connected to the gate of the second memory cell transistor,

a third word line electrically connected to the gate of the third memory cell transistor, and

a fourth word line electrically connected to the gate of the fourth memory cell transistor;

a sequencer configured to perform an erase operation on the memory cell transistors, the erase operation including an erase voltage apply operation and an erase verify operation, the erase voltage apply operation using a Gate-Induced-Drain-Leakage (GIDL) current,

wherein, during the erase operation,

a first voltage is applied to the first word line,

a second voltage different from the first voltage is applied to the second word line,

a third voltage is applied to the third word line, and

a fourth voltage different from the third voltage is applied to the fourth word line.