CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of the plurality of memory cells to be programmed to a target voltage level representing a first programming level;
causing, at a first time, first data to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level;
causing, at a second time, the cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level; and
executing, in view of the second data, a level shifting operation associated with the memory cell.
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