US 12,254,927 B2
In-line programming adjustment of a memory cell in a memory sub-system
Sheyang Ning, San Jose, CA (US); Lawrence Celso Miranda, San Jose, CA (US); Zhengyi Zhang, San Jose, CA (US); and Tomoko Ogura Iwasaki, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 3, 2024, as Appl. No. 18/654,697.
Application 18/654,697 is a continuation of application No. 17/670,037, filed on Feb. 11, 2022, granted, now 12,014,778.
Claims priority of provisional application 63/225,772, filed on Jul. 26, 2021.
Claims priority of provisional application 63/209,592, filed on Jun. 11, 2021.
Claims priority of provisional application 63/166,474, filed on Mar. 26, 2021.
Prior Publication US 2024/0290389 A1, Aug. 29, 2024
Int. Cl. G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of the plurality of memory cells to be programmed to a target voltage level representing a first programming level;
causing, at a first time, first data to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level;
causing, at a second time, the cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level; and
executing, in view of the second data, a level shifting operation associated with the memory cell.