US 12,254,926 B2
Memory device with fast write mode to mitigate power loss
Yu-Chung Lien, San Jose, CA (US); Juane Li, Milpitas, CA (US); Sead Zildzic, Jr., Folsom, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 3, 2022, as Appl. No. 17/817,288.
Prior Publication US 2024/0046990 A1, Feb. 8, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/3459 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
detect a condition associated with power supplied to the memory device;
detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device;
determine that a number of program/erase cycles, associated with a memory block to which data is to be written in connection with the one or more pending write operations, is less than or equal to a threshold;
switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on:
detecting the condition,
detecting the one or more pending write operations, and
determining that the number of program/erase cycles is less than or equal to the threshold; and
perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.