US 12,254,924 B2
Differentiable content addressable memory
Giacomo Pedretti, Cernusco sul Naviglio (IT); Catherine Graves, Milpitas, CA (US); Sergey Serebryakov, Milpitas, CA (US); and John Paul Strachan, Houston, TX (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, Houston, TX (US)
Filed on Jul. 28, 2022, as Appl. No. 17/876,471.
Prior Publication US 2024/0046988 A1, Feb. 8, 2024
Int. Cl. G11C 7/16 (2006.01); G06F 18/22 (2023.01); G06N 3/08 (2023.01); G11C 7/06 (2006.01); G11C 15/04 (2006.01); H03M 1/18 (2006.01)
CPC G11C 15/04 (2013.01) [G06F 18/22 (2023.01); G06N 3/08 (2013.01); G11C 7/062 (2013.01); G11C 7/16 (2013.01); H03M 1/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A differential content addressable memory (dCAM) array comprising:
a plurality of rows and columns of dCAM cells, wherein each row of dCAM cells include a high match line and a low match line;
a sense circuit electrically connected to the high match line and low match line, wherein the sensing circuit comprises:
a transimpedance amplifier (TIA) configured to sense a match line current on the low match line, and
an analog to digital converter (ADC) configured to sense an output voltage of the TIA and a match line voltage of the high match line; and
a digital to analog converter (DAC), electrically connected to each column of dCAM cells.