US 12,254,923 B2
Nonvolatile SRAM
Perng-Fei Yuh, Walnut Creek, CA (US); Jui-Che Tsai, Tainan (TW); Hiroki Noguchi, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 2, 2023, as Appl. No. 18/149,149.
Application 18/149,149 is a continuation of application No. 17/094,307, filed on Nov. 10, 2020, granted, now 11,545,218.
Claims priority of provisional application 62/955,531, filed on Dec. 31, 2019.
Prior Publication US 2023/0147686 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 11/16 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 14/00 (2006.01)
CPC G11C 14/0081 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
an SRAM cell having a first storage node selectively connectable to a first bit line in response to a control signal received on a first word line, and a second storage node selectively connectable to a first bit line bar in response to the control signal received on the first word line;
an MRAM cell including a first MTJ selectively connectable to the first storage node of the SRAM cell in response to a control signal received on a second word line, and a second MTJ selectively connectable to the second storage node of the SRAM cell in response to the control signal received on the second word line, wherein the first and second MTJs are connected to a second bit line;
wherein the second bit line is configured to receive an MRAM bit line control signal to connect a first terminal of the first MTJ and a first terminal of the second MTJ to a first voltage level, and thereafter the second word line is configured to receive an MRAM word line control signal to connect the first and second MTJs to the first and second storage nodes, respectively; and
wherein the second bit line is configured to receive the MRAM bit line control signal to connect the first terminal of the first MTJ and the first terminal of the second MTJ to a second voltage level, and thereafter the second word line is configured to receive the MRAM word line control signal to connect the first and second MTJs to the first and second storage nodes, respectively.