US 12,254,920 B2
Static random access memory circuit and read/write operation method thereof
Bing-Chen Wu, New Taipei (TW); Shuo-Hong Hung, New Taipei (TW); and Chung-Chieh Chen, New Taipei (TW)
Assigned to UPBEAT TECHNOLOGY Co., Ltd, New Taipei (TW)
Filed by UPBEAT TECHNOLOGY Co., Ltd, New Taipei (TW)
Filed on Jan. 5, 2023, as Appl. No. 18/093,771.
Claims priority of provisional application 63/296,883, filed on Jan. 6, 2022.
Claims priority of application No. 111148020 (TW), filed on Dec. 14, 2022.
Prior Publication US 2023/0215492 A1, Jul. 6, 2023
Int. Cl. G11C 11/408 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A static random access memory circuit comprising:
a plurality of memory units arranged in M columns and N rows;
M bit lines, each of which is electrically connected to N memory units located in a corresponding one of the M columns;
N row-voltage selection lines, each of which is electrically connected to M memory units located in a corresponding one of the N rows;
N word lines, each of which is electrically connected to the M memory units located in the corresponding one row; and
a control circuit, comprising:
a controller;
a voltage source providing a first voltage and a second voltage;
a voltage selection module electrically connected to the controller, the voltage source, and the N row-voltage selection lines, wherein the voltage selection module selectively transmits one of the first voltage and the second voltage to at least an nth row-voltage selection line of the N row-voltage selection lines, and transmits the second voltage to the row-voltage selection lines except the at least the nth row-voltage selection line;
a word-line driving module electrically connected to the controller and the N word lines; and
a bit-line driving module electrically connected to the controller and the M bit lines, wherein M, N, and n are positive integers, and n is smaller than or equal to N, wherein during an access period,
the voltage selection module transmits the first voltage to the at least the nth row-voltage selection line during a boost period, and
the voltage selection module transmits the second voltage to the at least the nth row-voltage selection line before and after the boost period,
wherein the boost period is shorter than the access period, and a read operation or a write operation is performed during the access period.